Design of Speech Recognition Co-Processor for the Embedded Implementation

This paper presents the design of high performance co-processor - MSAC (multiplier square accumulate calculation) co-processor for the embedded speech recognition of CHMM (Continuous Hidden Markov Model) with the dedicated hardware of Mahalanobis distance algorithm to finish the most computation intensive operations in the speech recognition flow. The co-processor could be used both off-chip controlled by MCU and on-chip as an IP core for IP based SOC design. The proposed MSAC co-processor has been designed and implemented in ASIC cell-based approach using 0.18 um UMC technology. By using this co-processor, the clock of system´s main processor, such as ARM7, could be down to as low as 20 MHz to meet the real-time requirement for embedded speech recognition, and the die size is 1.7 x 1.7 mm² (including 4 K Words SRAM), thus to reduce the power consumption and the cost significantly.