DocumentCode :
298544
Title :
On ΣΔ signal processing remodulator complexity
Author :
Kershaw, Simon M. ; Summerfieid, S. ; Sandler, Mark B.
Author_Institution :
Dept. of Electron. & Electr. Eng., King´´s Coll., London, UK
Volume :
2
fYear :
1995
fDate :
30 Apr-3 May 1995
Firstpage :
881
Abstract :
There has recently been some interest in the emerging technique of Sigma Delta Signal Processing (SDSP) where direct processing of the bitstream is proposed as an alternative to the decimation-PCM processing-interpolation cycle required for DSP of ΣΔ converted signals. SDSP requires digital (re)modulation with a variety of wordlengths in the oversampled datastream; the prediction and control of the remodulator complexity is crucial in determining the relative value of SDSP in any given context. This paper addresses this issue in deriving a new method for reducing remodulator complexity and in obtaining its dependence on the datastream wordlength
Keywords :
VLSI; digital filters; sigma-delta modulation; ΣΔ signal processing; SDSP; bitstream direct processing; datastream wordlength; digital remodulation; oversampled datastream; remodulator complexity; Adders; Arithmetic; Costs; Educational institutions; Finite impulse response filter; Guidelines; Hardware; Interpolation; Signal processing; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
Type :
conf
DOI :
10.1109/ISCAS.1995.519905
Filename :
519905
Link To Document :
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