Title :
Analysis of simultaneous switching noise
Author_Institution :
Hyperstone Electron. GmbH, Konstanz, Germany
fDate :
30 Apr-3 May 1995
Abstract :
With increasing system speed and I/O-count a noise phenomenon known as ΔI-Noise becomes more important and emerges as a limiting factor for reliable high speed chip-to-chip interconnections. Using a simplified model for CMOS drivers, the main effects of ΔI-Noise are investigated analytically and the impact of the model´s key parameters on the noise magnitudes and the driver delay is shown
Keywords :
CMOS integrated circuits; delays; driver circuits; integrated circuit interconnections; integrated circuit noise; transient analysis; ΔI-noise; CMOS drivers; chip-to-chip interconnections; driver delay; limiting factor; noise magnitudes; simultaneous switching noise; Circuit noise; Delay effects; Differential equations; Driver circuits; Equivalent circuits; Integrated circuit interconnections; Power supplies; Semiconductor device modeling; Transient analysis; Voltage;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.519911
