An FPGA based reconfigurable coprocessor board utilizing a Mathematics of Arrays

Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms have been developed using a Mathematics of Arrays (MOA) and are optimal in the sense that they reduce normal array cartesian indexing operations to a series of primitive additions and offsets based on array shape. The method is simple yet powerful, produces algorithms which are provably correct, and are independent of dimensionality. Software implementations have been used to provide speedups on the order of 100% to the solution of heat transfer equations on a uniprocessor. We extend these methods to application designs for the Chameleon coprocessor