On using partial reset for pseudo-random testing

An inexpensive Design For Testability (DFT) technique, called Partial Reset (PR), was recently proposed to ease automatic test pattern generation of sequential circuits. In the present paper, we propose a new PR-like method. With this method, flip-flops to be reset are selected in order to ease pseudo-random testing of sequential circuits. Moreover, the control of these reset are condensed on a reduced set of input lines. Therefore, only a small number of additional primary inputs are required. This technique has been evaluated on a large subset of the 1989 ISCAS sequential benchmark circuits and promising results were obtained