Title :
190-MHz CMOS 4-Kbyte pipelined caches
Author :
Srivastava, Apoorv ; Koh, Yong-seon ; Sano, Barton ; Despain, Alvin M.
Author_Institution :
Dept. of Comput. Eng., California Univ., Los Angeles, CA, USA
fDate :
30 Apr-3 May 1995
Abstract :
In this paper we describe the design and implementation of a 190-MHz pipelined 4-Kbyte instruction and data cache. The caches are designed in 1.0-μm CMOS and measure 0.78×0.47 cm2. This paper describes the microarchitecture, cache timing, circuit implementation, and layout of both the instruction and the data cache. The key features of these caches are pipelined execution and the use of dynamic single-phase clock logic. We discuss the interface of this cache with the processor core and the off-chip controller. This paper also describes the pipelined structure of the cache and the miss detection and handling logic
Keywords :
CMOS memory circuits; cache storage; parallel architectures; pipeline processing; timing; 1.0 micron; 190 MHz; 4 KB; CMOS; cache timing; circuit implementation; dynamic single-phase clock logic; handling logic; microarchitecture; miss detection; pipelined caches; pipelined execution; CMOS logic circuits; Clocks; Computer aided instruction; Driver circuits; Microarchitecture; Multiplexing; Pipeline processing; Registers; Signal processing; Timing;
Conference_Titel :
Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
0-7803-2570-2
DOI :
10.1109/ISCAS.1995.519948
