DocumentCode
2986012
Title
Decreasing error floor in LDPC codes by parity-check matrix extensions
Author
Sharon, Eran ; Fainzilber, Orner ; Litsyn, Simon
Author_Institution
Sch. of Electr. Eng., Tel Aviv Univ., Ramat Aviv, Israel
fYear
2009
fDate
June 28 2009-July 3 2009
Firstpage
374
Lastpage
378
Abstract
High error floors in optimized irregular LDPC codes limit their usage in applications that require low error rates. We introduce new methods for lowering the error floor of LDPC codes, based on enhancing the code´s parity-check matrix with additional linearly dependent and independent parity-checks. We prove NP hardness of certain optimization problems related to proposed methods and provide upper bound on the number of parity-checks that need to be added. We show that the proposed methods can lower the error floor of the code significantly, by several orders of magnitude, at negligible or no rate penalty.
Keywords
error correction codes; optimisation; parity check codes; LDPC codes; NP-hard problem; code error floor; optimization problems; parity-check matrix extensions; Bipartite graph; Error analysis; Floors; Iterative decoding; Joining processes; Linear code; Optimization methods; Parity check codes; Sparse matrices; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory, 2009. ISIT 2009. IEEE International Symposium on
Conference_Location
Seoul
Print_ISBN
978-1-4244-4312-3
Electronic_ISBN
978-1-4244-4313-0
Type
conf
DOI
10.1109/ISIT.2009.5205738
Filename
5205738
Link To Document