• DocumentCode
    2986426
  • Title

    Frame Frequency Multiplier System for Stereo Video on Programmable Hardware

  • Author

    Fan, Haijin ; Yang, Fan ; Liao, Qingmin

  • Author_Institution
    Visual Inf. Process. Labotary, Tsinghua Univ., Shenzhen, China
  • fYear
    2009
  • fDate
    18-20 Jan. 2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A frame frequency multiplier system based on field programmable gate array (FPGA) for time-sequential stereo video is proposed in this paper. The system converts two standard 60 fields/sec interlaced NTSC videos captured by two cameras in different perspective views to a 120 frames/sec time-sequential progressive stereo video. Video synchronization signals are generated based on look-up tables according to the timing of stereo video and a novel ping-pong approach realized by first-in first-out (FIFO) memories is applied to control video data acquisition and transmission in the system. It can provide high quality and flicker-free 3-D stereo images and thus will bring the stereo video system wide applications.
  • Keywords
    data acquisition; field programmable gate arrays; frequency multipliers; stereo image processing; video signal processing; field programmable gate array; first-in first-out memories; flicker-free 3D stereo images; frame frequency multiplier system; interlaced NTSC videos; look-up tables; ping-pong approach; programmable hardware; time-sequential progressive stereo video; video data acquisition; video data transmission; Cameras; Eyes; Field programmable gate arrays; Frequency synchronization; Hardware; Humans; Image converters; Image quality; Liquid crystal displays; TV;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Network and Multimedia Technology, 2009. CNMT 2009. International Symposium on
  • Conference_Location
    Wuhan
  • Print_ISBN
    978-1-4244-5272-9
  • Type

    conf

  • DOI
    10.1109/CNMT.2009.5374537
  • Filename
    5374537