Power dissipation in a vertically integrated chip-scale atomic clock

The physics package of a vertically integrated chip-scale atomic clock, based on cesium, has recently been demonstrated at NIST. This device requires 69 mW of electrical power to maintain the vapor cell 34 K above the temperature of the baseplate. The physics package structure is analyzed by use of analytical thermal modeling and finite-element calculation. Improvements to the design are proposed to reduce the power consumption of the physics package alone to near 15 mW and of a full chip-scale atomic clock to below approximately 30 mW. Power consumption at this level will open the door to the use of atomic frequency references in portable, battery-operated applications such as wireless communications and global positioning.