An Adiabatic Single-Phase MTCMOS Scheme for Leakage Reduction in Nano-Scale CMOS Processes

With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage consumption has become an important concern in low power and high performance applications for nano-scale CMOS processes. This paper presents a MTCMOS (multi-threshold CMOS) power-gating scheme for single-phase adiabatic circuits, which minimizes leakage dissipations during sleep mode. The 8-bit full adder based on Improved CAL (Clocked Adiabatic Logic) circuits with the MTCMOS scheme is used to verify its leakage reduction. All circuits are simulated using 90nm Nano-CMOS technology with 0.15V low threshold voltage and 0.35V high threshold voltage, and 45nm Nano-CMOS technology with 0.12V low threshold voltage and 0.28V high threshold voltage. The simulations show leakage consumption can greatly be reduced by using the proposed MTCMOS power-gating technique compared with the conventional power-gating one.