Title :
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores
Author :
Ramanarayanan, Rajaraman ; Mathew, Sanu ; Erraguntla, Vasantha ; Krishnamurthy, Ram ; Gueron, Shay
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper describes a unified popcount/bitscanforward/bitscanreverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5 mW, targeted for 65 nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of ´1´s in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree to identify the bit-location of the 1st set bit when scanning the input in the forward and reverse directions. This circuit thus combines the functions of 3 separate units, enabling 26% reduction in total energy and 20% lower area, while achieving single-cycle latency & throughput.
Keywords :
CMOS integrated circuits; encoding; logic design; microprocessor chips; trees (mathematics); bitscan datapath unit; bitscanforward datapath circuit; bitscanreverse datapath circuit; compressor-based Wallace tree; encoding scheme; frequency 2.1 GHz; microprocessor execution cores; power 6.5 mW; power consumption; size 65 nm; unified popcount datapath circuit; word length 64 bit; Acceleration; Counting circuits; Delay; Encoding; Energy consumption; Hardware; Laboratories; Microprocessors; Throughput; Very large scale integration;
Conference_Titel :
VLSI Design, 2008. VLSID 2008. 21st International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-7695-3083-4
DOI :
10.1109/VLSI.2008.75
