Optimizing the critical loop in the H.264/AVC CABAC decoder

Author

Eeckhaut, Hendrik ; Christiaens, Mark ; Stroobandt, Dirk ; Nollet, Vincent

Author_Institution

Dept. of Electron. & Inf. Syst., Ghent Univ.

fYear

2006

fDate

Dec. 2006

Firstpage

113

Lastpage

118

Abstract

This paper presents an innovative hardware implementation of the H.264/AVC CABAC binary arithmetic decoder and context modeler capable of decoding one symbol per clock cycle at high clock frequencies while maintaining a slim hardware footprint. This was achieved by substantially decreasing the latency of the central feedback loop through extensive use of speculative prefetching and aggressive pipelining. Actual synthesis results targeted at the state-of-the-art FPGA families show that our approach results in a fast and compact IP core, ideal for a SoC H.264/AVC implementation

Keywords

digital arithmetic; field programmable gate arrays; pipeline processing; storage management; system-on-chip; video coding; FPGA; H.264/AVC CABAC decoder; SoC; aggressive pipelining; binary arithmetic decoder; central feedback loop; context modeler; critical loop optimization; field programmable gate array; one symbol per clock cycle; slim hardware footprint; speculative prefetching; Arithmetic; Automatic voltage control; Clocks; Context modeling; Decoding; Delay; Feedback loop; Frequency; Hardware; Prefetching;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on

Conference_Location

Bangkok

Print_ISBN

0-7803-9729-0

Electronic_ISBN

0-7803-9729-0

Type

conf

DOI

10.1109/FPT.2006.270301

Filename

4042423