High-Q Integrated Inductor Using Post-CMOS Selective Grown Porous Silicon (SGPS) Technique for RFIC Applications

This paper reports a new category of high-Q integrated inductor which is realized using post-CMOS selective grown porous silicon (SGPS) technique. The SGPS technique is used to effectively reduce low-resistivity silicon substrate loss. Different from other porous silicon (PS) based inductor techniques, this SGPS technique is completely post-CMOS based. The inductors are fabricated in standard RF CMOS process firstly and then Q-factors are improved through our proposed post-CMOS SGPS technique. For a 2.1 nH inductor fabricated in a standard 0.35 mum RF CMOS process, a 105% increase (from 9.5 to 19.4) in peak Q factor is obtained. Furthermore, a 2.45 GHz VCO using proposed SGPS inductor achieves 7.2 dBc phase noise improvement at 100 kHz frequency offset.