Sigma-delta based clock recovery using on-chip PLL in FPGA

A clock and data recovery (CDR) circuit is proposed based on the sigma-delta quantization. The phase of the new CDR circuit is adjusted by a sigma-delta modulated reference clock that increases the stability of the system and can easily interface with PLL cores embedded in FPGAs. The approximate linear model of the proposed CDR is analyzed for SONET/SDH applications to evaluate its performance. The measurement shows that the jitter tolerance meets the ITU-T requirement with a high margin of 0.3UI. The commercial equipment has been developed using a single FPGA chip based on the SDM-CDR