DocumentCode
2986990
Title
Digital RF Processor (DRP) for Mobile Phones
Author
Staszewski, R. Bogdan ; Muhammad, Khurram ; Eliezer, Oren
Author_Institution
Texas Instrum., Dallas
fYear
2007
fDate
3-5 June 2007
Firstpage
181
Lastpage
184
Abstract
RF circuits for wireless applications have recently migrated to low-cost digital nanoscale CMOS processes, which are optimized for digital logic and SRAM memory, but are unfriendly for conventional analog and RF designs. We present fundamental techniques, recently developed for wireless RF transceivers, that transform the RF and analog circuit design complexities into the digital domain, where it may benefit from the process node scaling and the design automation environment. The all-digital phase locked loop, the all-digital control of phase and amplitude of a polar transmitter, and the direct RF sampling techniques in the receiver allow great flexibility in reconfigurable radio design. The ideas presented have been realized in several commercial digital RF processors offered by Texas Instruments, including single-chip Bluetooth and GSM radios.
Keywords
CMOS logic circuits; CMOS memory circuits; SRAM chips; analogue integrated circuits; mobile radio; phase locked loops; software radio; transceivers; DRP; SRAM memory; Texas Instruments; all-digital control; all-digital phase locked loop; analog circuit design; digital RF processor; digital logic memory; digital nanoscale CMOS process; direct RF sampling technique; mobile phone; polar transmitter; reconfigurable radio design; wireless RF transceiver; Analog circuits; CMOS logic circuits; CMOS process; Design automation; Design optimization; Logic design; Mobile handsets; Radio frequency; Random access memory; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE
Conference_Location
Honolulu, HI
ISSN
1529-2517
Print_ISBN
1-4244-0530-0
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2007.380860
Filename
4266408
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