Low Power Hardware Architecture for VBSME Using Pixel Truncation

Author

Bahari, Asral ; Arslan, Tughrul ; Erdogan, Ahmet T.

Author_Institution

Univ. of Edinburgh, Edinburgh

fYear

2008

fDate

4-8 Jan. 2008

Firstpage

389

Lastpage

395

Abstract

This paper presents an efficient architecture to implement low power variable block size motion estimation (VBSME) using full search. Power reduction is achieved by performing the search in two steps: low pixel resolution and full pixel resolution. We analysed the computation and memory units needed to support these two search modes. The proposed architecture reduces the total energy consumption by 50% with 6% additional area compared to the conventional architecture.

Keywords

image resolution; integrated memory circuits; low-power electronics; memory architecture; motion estimation; energy consumption; full-pixel resolution; full-search motion estimation; low-pixel resolution; low-power hardware architecture; memory architecture; pixel truncation; variable block size motion estimation; Bandwidth; Batteries; Computer architecture; Costs; Degradation; Energy consumption; Energy resolution; Hardware; Motion estimation; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2008. VLSID 2008. 21st International Conference on

Conference_Location

Hyderabad

ISSN

1063-9667

Print_ISBN

0-7695-3083-4

Type

conf

DOI

10.1109/VLSI.2008.100

Filename

4450532

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2987073