DocumentCode
2987095
Title
Configuration memory based dynamic coarse grained reconfigurable multicore architecture
Author
Padole, Dinesh ; Hiware, Rahul
Author_Institution
Dept. of Electron. Eng., G.H. Raisoni Coll. of Eng., Nagpur, India
fYear
2013
fDate
22-25 Oct. 2013
Firstpage
1
Lastpage
5
Abstract
Hardware Re-configurability is providing solution to use same hardware for different application with and optimized hardware utilization. This leads towards small size and power efficient system design. Coarse-grained Architecture (CGRA) is one of the reconfigurable system use by byte computing. This paper proposed and configuration memory based CGRA system which can change the hardware configuration dynamically according to applications. Author has designed CGRA system with 4×4 Processing Elements (PE) and configured for 4 point FFT application. A suitable Data flow diagram has developed for the application. The results are presented in the paper.
Keywords
data flow computing; fast Fourier transforms; multiprocessing systems; reconfigurable architectures; CGRA system; FFT application; PE; byte computing; configuration memory; data flow diagram; dynamic coarse grained reconfigurable multicore architecture; hardware configuration; hardware re-configurability; processing elements; Arrays; Hardware; Indexes; Memory management; Microprocessors; Program processors; CGRA; Multicore systems;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2013 - 2013 IEEE Region 10 Conference (31194)
Conference_Location
Xi´an
ISSN
2159-3442
Print_ISBN
978-1-4799-2825-5
Type
conf
DOI
10.1109/TENCON.2013.6719038
Filename
6719038
Link To Document