FPGA acceleration of the tate pairing in characteristic 2

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using theeta_T method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field