DocumentCode :
2987269
Title :
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers
Author :
Yu, Yinlei ; Brien, Cameron ; Malik, Sharad
Author_Institution :
Princeton Univ., Princeton
fYear :
2008
fDate :
4-8 Jan. 2008
Firstpage :
461
Lastpage :
468
Abstract :
Most contemporary SAT solvers use a conjunctive-normal-form (CNF) representation for logic functions due to the availability of efficient algorithms for this form, such as deduction through unit propagation and conflict driven learning using clause resolution. The use of CNF generally entails transformation to this form from other representations such as logic circuits (Tseitin, 1970). However, this transformation results in loss of information such as direction of signal flow and observability of signals at circuit outputs (Een, 2003)(Fu, 2005). This has prompted the development of various circuit-based solvers (Ganai et al., 2002), hybrid CNF+circuit-based solvers (Fu, 2005), as well as augmented CNF solvers (Een, 2003). Having the circuit available provides for additional capabilities at a cost, and thus requires careful analysis to determine the viability of each approach. This paper highlights one specific capability provided by a circuit: the ability to consider reconvergent paths in unit propagation. Unit propagation is the workhorse of contemporary SAT solvers, thus any improvement to this has significant practical potential. We first demonstrate that the Tseitin circuit-to-CNF transformation limits backward unit propagation and how additional implications can be derived when unit propagation across multiple paths is considered. Next, we show how these implications can be exploited by statically learning clauses during circuit pre-processing. The results of the practical implementation of these algorithms show that the static learning can provide significant speed-up on several classes of benchmark circuits. Finally, we discuss how this work compares with other circuit-based approaches, especially those arising from the automatic-test-pattern-generation (ATPG) community (e.g. recursive learning) and circuit and non- circuit based pre-processors.
Keywords :
automatic test pattern generation; computability; electronic design automation; logic design; ATPG; CNF SAT solvers; automatic-test-pattern-generation; backward unit propagation; circuit preprocessing; circuit reconvergence; conjunctive-normal-form representation; non-circuit based pre-processors; reconvergent paths; static learning; Algorithm design and analysis; Automatic test pattern generation; Calculus; Costs; Decision making; Logic circuits; Logic functions; Observability; Signal resolution; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2008. VLSID 2008. 21st International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
0-7695-3083-4
Type :
conf
DOI :
10.1109/VLSI.2008.90
Filename :
4450543
Link To Document :
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