Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs

This paper describes an activity-based strategy for estimating the average power dissipation of hard DSP and multiplier blocks embedded in FPGAs. We identified two technical challenges in creating a tool flow to do this: (1) estimating the activity of all nodes in designs containing DSP blocks, and (2) estimating the average power dissipated within the DSP block quickly and accurately. In this paper, we compare several methods to address each of these two challenges. We conclude with a description of our complete power estimation flow