Hardware synthesis of artificial neural networks using field programmable gate arrays and fixed-point numbers

A three-layer fully-connected feedforward neural network with 35 input neurons, 10 hidden neurons, and 26 output neurons has been developed and implemented directly in hardware. The digital neurons use 12-bit two´s complement fixed-point weights and symmetric saturating linear activation functions. The hidden layer and output layer contain 360 and 286 12-bit weights respectively. The neural network was developed with VHDL and synthesized for an XC2V4000-6BF957 X iVirtex-2 FPGA. All calculations within each neural layer are performed in parallel. The neural network was configured and trained to solve the classic character recognition problem. The network was trained in MATLAB using floating-point numbers and an uncorrupted character set. The trained network achieved a 100% recognition rate on the perfect characters as well as characters that had up to 29% of their pixels flipped. When the floating-point computations from MATLAB were performed instead with 12-bit fixed-point weights in the Xilinx FPGA, for the characters tested to date, uncorrupted character recognition remained at 100% and noisy character recognition was not significantly affected by the loss of precision.