DocumentCode
2987381
Title
FPGA implementation for an iris biometric processor
Author
Jimenez, Judith Liu ; Reillo, Raul Sanchez ; Lindoso, Almudena ; Hurtado, Oscar Miguel
Author_Institution
Dept. of Electron. Technol., Univ. Carlos III, Madrid
fYear
2006
fDate
Dec. 2006
Firstpage
265
Lastpage
268
Abstract
Biometrics is nowadays one of the most promising techniques in authentication. Biometrics intends to identify a user by his/her physical and/or behavioural characteristic. Among all Biometric techniques, Iris recognition stands out, as its error rates are one of the lowest. The authors propose in this paper a hardware implementation based on FPGA for an iris biometric processor. By this solution a reduction of the processing time is obtained and security levels of the whole system are increased due to the reduction of software involved
Keywords
biometrics (access control); feature extraction; field programmable gate arrays; image recognition; feature extraction; field programmable gate arrays; identification device; iris biometric processor; iris recognition; Authentication; Biometrics; Cameras; Feature extraction; Field programmable gate arrays; Gabor filters; Hamming distance; Iris recognition; Microelectronics; Security;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on
Conference_Location
Bangkok
Print_ISBN
0-7803-9729-0
Electronic_ISBN
0-7803-9729-0
Type
conf
DOI
10.1109/FPT.2006.270324
Filename
4042446
Link To Document