CPW and discontinuities modeling for circuit design up to 110 GHz in SOI CMOS technology

Author

Siligaris, A. ; Mounet, C. ; Reig, B. ; Vincent, P.

Author_Institution

CEA, Grenoble

fYear

2007

fDate

3-5 June 2007

Firstpage

295

Lastpage

298

Abstract

This paper presents a new modeling method for integrated coplanar wave guides (CPW) and CPW discontinuities implemented in silicon on insulator (SOI) CMOS technology. Empirical equations, which are fitted to 3D EM simulations, are used to describe the electrical behavior of CPW as a function of the line´s geometrical parameters. The models are validated through measurements up to 110 GHz. Thanks to accurate full wave simulations, discontinuities such as underpasses, 90deg bends, and tee and cross junctions are improved, and electrical models are developed. All models are easily implemented in commercial CAD tools. Finally, a 60 GHz band-pass filter is designed applying the described models and the simulations are compared to measurements.

Keywords

band-pass filters; coplanar waveguides; microwave filters; silicon-on-insulator; CPW; SOI CMOS technology; band-pass filter; circuit design; discontinuities modeling; full wave simulations; integrated coplanar wave guides; silicon on insulator; CMOS technology; Circuit simulation; Circuit synthesis; Coplanar waveguides; Design automation; Equations; Integrated circuit technology; Semiconductor device modeling; Silicon on insulator technology; Solid modeling; 60 GHz; 90Â° bend; CMOS millimeter wave integrated circuit; Silicon on insulator; coplanar wave guide; high frequency modeling; tee junction; underpass;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE

Conference_Location

Honolulu, HI

ISSN

1529-2517

Print_ISBN

1-4244-0530-0

Electronic_ISBN

1529-2517

Type

conf

DOI

10.1109/RFIC.2007.380886

Filename

4266434