DocumentCode
2987524
Title
Asymmetric DC Offsets and IIP2 in the Presence of LO Leakage in a Wireless Receiver
Author
Elahi, Imtinan ; Muhammad, Khurram
Author_Institution
Texas Instrum. Inc., Dallas
fYear
2007
fDate
3-5 June 2007
Firstpage
313
Lastpage
316
Abstract
We present mathematical analysis to prove that LO leakage at the input of RF circuits in the presence of finite IIP3 results in asymmetry in DC offsets and IIP2 between in-phase and quadrature channels in a wireless receiver. The asymmetry in IIP2 causes effective IIP2 of the receiver to be at best only 3 dB higher than the smaller of two IIP2 values. Measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process is also presented to support mathematical analysis.
Keywords
CMOS integrated circuits; cellular radio; mathematical analysis; packet radio networks; radio receivers; RF circuits; asymmetric DC offsets; digital CMOS process; mathematical analysis; quadband GSM-GPRS receiver; quadrature channels; wireless receiver; CMOS process; Circuits; Clocks; Distortion measurement; GSM; Ground penetrating radar; Low pass filters; Mathematical analysis; Radio frequency; Receivers; Circuits; frequency; intermodulation distortion; mixers; radio receivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE
Conference_Location
Honolulu, HI
ISSN
1529-2517
Print_ISBN
1-4244-0530-0
Electronic_ISBN
1529-2517
Type
conf
DOI
10.1109/RFIC.2007.380890
Filename
4266438
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