A leakage aware design methodology for power-gated programmable architectures

One popular technique to deal with increasing leakage current in modern FPGAs is to group logic into sleeper cells and isolate them from power rails whenever they are inactive in time and space. However, such architectures demand novel methodology to effectively layout the design, so that maximum sleeper cells can be shut down. In this work, we present a slicing tree based simulated annealing methodology that grooms the various blocks of a design, so that they can be put into power-down mode either in temporal or spatial domain. Our technique nicely fits into a power-aware design flow targeting standby/portable applications where substantial portion of the design sits idle for a long period of time. We also propose a novel technique to include BRAMs into the presented methodology. Our experiments shows up to a maximum 43% of leakage savings in some benchmarks