• DocumentCode
    2987615
  • Title

    An Acceleration and Optimization Method for Optical Reconfiguration

  • Author

    Watanabe, Minoru ; Yamaguchi, Naoki

  • Author_Institution
    Shizuoka Univ., Shizuoka
  • fYear
    2008
  • fDate
    4-8 Jan. 2008
  • Firstpage
    607
  • Lastpage
    612
  • Abstract
    Optically reconfigurable gate arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much larger than those of currently available VLSI circuits. Because circuits implemented on a gate array must often be changed using virtual circuits stored in a holographic memory, rapid reconfiguration is necessary to reduce the reconfiguration overhead. A simple means to realize a short reconfiguration time in ORGAs is to implement a high-power laser array. However, such an array presents the disadvantages of high power consumption, large implementation space, high cost, and so on. Therefore, this paper presents an acceleration method to increase ORGAs´ reconfiguration frequency without the necessity for any increase of laser power. This technique also includes optimization between the number of reconfiguration contexts and the reconfiguration frequency. The description in this paper clarifies the advantages using simulation and experimental results.
  • Keywords
    VLSI; field programmable gate arrays; logic design; optical storage; reconfigurable architectures; VLSI circuits; high power consumption; high-power laser array; holographic memory; optical reconfiguration; optically reconfigurable gate arrays; storage capacity; virtual circuits; Acceleration; Circuits; Costs; Energy consumption; Frequency; Holographic optical components; Holography; Optical arrays; Optimization methods; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2008. VLSID 2008. 21st International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-3083-4
  • Type

    conf

  • DOI
    10.1109/VLSI.2008.26
  • Filename
    4450565