Design and implementation of a CMOS non-restoring divider

The process of binary division is the most complicated and slow among all the binary arithmetic operation. Although division is an infrequent operation compared to addition and multiplication, its longer latency makes division dissipate a significant amount of energy. This longer latency is due to the introduction of additional condition checking, which is necessary for correct functioning. The energy dissipation of dividers is comparable to that of floating-point adders. In order to achieve high performance with minimum energy dissipation, it is necessary to have efficient division algorithms. This paper presents an implementation of one such algorithm. The proper choice of the divider architecture is therefore essential for achieving low-power dissipation, high design flexibility and high reusability of existing building blocks of digital arithmetic and logic units.