DocumentCode
2987903
Title
Hardware architectures for Monte-Carlo based financial simulations
Author
Thomas, David B. ; Bower, Jacob A. ; Luk, Wayne
Author_Institution
Dept. of Comput., Imperial Coll. London
fYear
2006
fDate
Dec. 2006
Firstpage
377
Lastpage
380
Abstract
This paper presents a methodology and the results of implementing Monte-Carlo financial simulations in reconfigurable devices. Five different Monte-Carlo simulations are explored, including log-normal price movements, correlated asset value-at-risk calculation, and price movements under the GARCH model. Our results show that hardware implementations from our approach on a Xilinx Virtex-4 XC4VSX55 device run on-average 80 times faster than software on a 2.66GHz PC
Keywords
Monte Carlo methods; field programmable gate arrays; financial data processing; microprocessor chips; reconfigurable architectures; 2.66 GHz; GARCH model; Monte-Carlo financial simulations; Xilinx Virtex-4 XC4VSX55 device; correlated asset value-at-risk calculation; hardware architectures; log-normal price movements; reconfigurable devices; Communication channels; Computational modeling; Computer architecture; Costs; Delay; Electronic equipment testing; Field programmable gate arrays; Hardware; Pricing; Random number generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Technology, 2006. FPT 2006. IEEE International Conference on
Conference_Location
Bangkok
Print_ISBN
0-7803-9729-0
Electronic_ISBN
0-7803-9729-0
Type
conf
DOI
10.1109/FPT.2006.270352
Filename
4042474
Link To Document