Title :
The design of an all digital phase-locked loop
Author_Institution :
Electrospace Syst. Inc., Richardson, TX, USA
Abstract :
A method for synthesizing an all digital phase-locked loop is proposed. The design is based on the digitization of a continuous system whereby the s-plane poles and zeros of a specified differential equation are mapped to the z-plane poles and zeros of a corresponding difference equation using the matched z-transform method. The critical parameters are specified and their influence on loop performance is noted. The performance of the digital loop is shown through analysis and computer simulations
Keywords :
Z transforms; digital circuits; digital simulation; phase-locked loops; poles and zeros; PLL; all digital phase-locked loop; computer simulations; continuous system digitisation; digital loop; matched z-transform method; poles; s-plane; specified differential equation; z-plane; zeros; Additive white noise; Equations; Filters; Phase detection; Phase locked loops; Phase noise; Poles and zeros; Steady-state; Tracking loops; Voltage-controlled oscillators;
Conference_Titel :
Vehicular Technology Conference, 1988, IEEE 38th
Conference_Location :
Philadelphia, PA
DOI :
10.1109/VETEC.1988.195403
