Title :
FOLM-planner: A new floorplanner with a frame overlapping floorplan model suitable for SOG (sea-of-gates) type gate arrays
Author :
Murofushi, M. ; Yamada, M. ; Mitsuhashi, T.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM-planner is based on a ´frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer.<>
Keywords :
circuit layout CAD; logic CAD; logic arrays; FOLM-planner; floorplanner; force directed method; frame overlapping floorplan model; frame reshaping; gate arrays; net length; sea-of-gates; Chip scale packaging; Circuits; Lapping; Large scale integration; Logic; Routing; Shape; Timing; Ultra large scale integration; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129863
