• DocumentCode
    298803
  • Title

    Synthesis of asynchronous circuits-testing unique circuit behavior of signal transition graphs

  • Author

    Hsia, Calvin J A ; Chen, C. Y Roger

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
  • Volume
    2
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    1074
  • Abstract
    An important work related to the synthesis of asynchronous circuits from a signal transition graph (STG) specification is studied in this paper. The work is to test the satisfaction of one-token restriction. The one-token restriction is essential for an STG to avoid possible ambiguity in a behavioral specification. A graph reduction method which uses five reduction operations: series, parallel, unique-cycle, group-collapse, and conflict-block reductions, is proposed to achieve the task. Experimental results show that our proposed techniques are also very efficient for STGs of very large sizes
  • Keywords
    asynchronous circuits; logic design; signal flow graphs; asynchronous circuits; behavioral specification; circuit behavior; conflict-block reductions; graph reduction method; logic synthesis; one-token restriction; signal transition graphs; Asynchronous circuits; Benchmark testing; Circuit synthesis; Circuit testing; Protocols; Samarium; Signal synthesis; Sufficient conditions; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-7803-2570-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.1995.520332
  • Filename
    520332