The AES Encryption and Decryption Realization Based on FPGA

Author

Lan, Luan

Author_Institution

Dept. of Inf. Security, Guizhou Univ., Guizhouguiyang, China

fYear

2011

fDate

3-4 Dec. 2011

Firstpage

603

Lastpage

607

Abstract

With the development of networking technology, Hardware encryption technology will become an irreplaceable safety technology. In this paper, a method of AES encryption and decryption algorithm implemented on the same FPGA is presented, where a 128-bit key size mode is implemented, Modelsim simulation test results are demonstrated, the correctness of logic function of the system is verified, and system resource occupancy is presented and briefly analyzed to verify the reliability of the method. Practice proving it is an optimized hardware encryption and decryption method.

Keywords

cryptography; field programmable gate arrays; logic simulation; logic testing; AES decryption algorithm; AES encryption algorithm; FPGA; Modelsim simulation test; hardware encryption technology; logic function; networking technology; system resource occupancy; word length 128 bit; Algorithm design and analysis; Encryption; Field programmable gate arrays; Hardware; Hardware design languages; Logic gates; Random access memory; EDA QuartusII verilog HDL Simulation Modelsim AES Optimization System Resource;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence and Security (CIS), 2011 Seventh International Conference on

Conference_Location

Hainan

Print_ISBN

978-1-4577-2008-6

Type

conf

DOI

10.1109/CIS.2011.138

Filename

6128194