Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators

In this paper, we present a design methodology based on a multi-simulator approach instead of using co-simulation. We based our study on a phase locked loop (PLL) used in RF transceivers for frequency synthesis. We used Simulink as block diagram simulator, ADVance MS (ADMS) as behavioral simulator and Eldo as transistor-level simulator. The proposed results show the accuracy and simulation time for each description level.