High performance RF SOI MOSFET varactor modeling and design

This paper presents an RF model of an accumulation-mode MOS varactor with a high capacitance tuning range in a multi-finger layout. This model is based on the physical parameters of the device, and it can describe the voltage dependent capacitance, as well as the parasitic circuit elements. It employs a single topology with lumped elements derived from the device, so that it can be easily integrated into common circuit simulators, as well as directly linked to a p-cell. A Verilog-A model of the varactor has been presented and verified with Cadence for circuit simulation. Good agreements between measured data and simulation results were obtain in the frequency range of 0.1 to 10 GHz by de-embedding from the test frame.