VLSI implementation of a wavelet image compression technique using replicated coding/decoding cells

In this paper a wavelet based algorithm, its architecture and VLSI implementation for a hierarchical image coding technique is presented. The algorithm is based on a biorthogonal expansion involving a pair of mother wavelets, which are 2D discrete pyramid-shaped versions of the piecewise linear B-spline. The implementation is block oriented and includes a post-processing zerotree coding scheme to obtain further compression. The wavelet transform is computed using a previously designed array of replicated cells. The complementary architecture for the zerotree coding scheme is introduced in this paper