• DocumentCode
    2988213
  • Title

    Partitioning algorithms for layout synthesis from register-transfer netlists

  • Author

    Wu, A.C.H. ; Gajski, D.D.

  • Author_Institution
    Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
  • fYear
    1990
  • fDate
    11-15 Nov. 1990
  • Firstpage
    144
  • Lastpage
    147
  • Abstract
    A sliced-layout architecture is presented to alleviate the problems of the general bit-sliced layouts. Also described are partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between logic blocks. This approach improves the overall area utilization and minimizes the total wire length.<>
  • Keywords
    circuit layout CAD; I/O pin locations; critical paths; floorplan; general bit-sliced layouts; layout synthesis; overall area utilization; partitioning algorithms; register-transfer netlists; sliced-layout architecture; total wire length; Adders; Counting circuits; Flip-flops; Integrated circuit synthesis; Latches; Multiplexing; Partitioning algorithms; Registers; Routing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-2055-2
  • Type

    conf

  • DOI
    10.1109/ICCAD.1990.129864
  • Filename
    129864
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2988213