Abstract :
High power-performance ratio is the most important factor in high-performance computing, whose performance is limited by its power budget. A SuperH (SH) embedded processor core, SH-X3, implemented in a 90-nm CMOS process running at 600 MHz achieved 1080 Dhrystone MIPS, 4.2 GFLOPS, and 55 M polygons/s. Its power performance ratio reaches to as high as 3000 MIPS/W. It is, therefore, a candidate processor for high-performance computing. This paper focuses on the SH processors´ low power features, floating-point architecture and performance, and applicability to the high- performance computing.
Keywords :
CMOS integrated circuits; microprocessor chips; parallel processing; CMOS; SH-X3; SuperH embedded processor core; floating-point architecture; frequency 600 MHz; high-performance computing; size 90 nm; CMOS process; Computer architecture; Delay; Distributed power generation; Embedded computing; Frequency; High performance computing; Instruction sets; Laboratories; Pipelines;
