Empirical study of parallel trace-driven LRU cache simulators

Author

Nicol, David ; Carr, Eric

Author_Institution

Dept. of Comput. Sci., Coll. of William & Mary, Williamsburg, VA, USA

fYear

1995

fDate

14-16 Jun 1995

Firstpage

166

Lastpage

169

Abstract

This paper reports on the performance of four parallel algorithms for simulating an associative cache operating under the LRU (Least-Recently-Used) replacement policy. Three of the algorithms are implemented on the MasPar MP-2. Another algorithm is a parallelization of an efficient serial algorithm on the Intel Paragon. We assess the strengths and weaknesses of these algorithms as a function of problem size and characteristics, and compare their performance on traces derived from execution of three SPEC92 benchmark programs

Keywords

cache storage; content-addressable storage; parallel algorithms; storage management; virtual machines; Intel Paragon; Least-Recently-Used replacement policy; MasPar MP-2; SPEC92 benchmark programs; associative cache; efficient serial algorithm; parallel algorithms; parallel trace-driven LRU cache simulators; Computational modeling; Computer science; Computer simulation; Data structures; Databases; Drives; Educational institutions; File systems; Parallel algorithms; Zinc;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Simulation, 1995. (PADS'95), Proceedings., Ninth Workshop on (Cat. No.95TB8096)

Conference_Location

Lake Placid, NY

Print_ISBN

0-8186-7120-3

Type

conf

DOI

10.1109/PADS.1995.404304

Filename

404304