DocumentCode
2988910
Title
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
Author
Palumbo, Francesca ; Pani, Danilo ; Pilia, Alessandro ; Raffo, Luigi
Author_Institution
DIEE Dept. of Electr. & Electron. Eng., Univ. of Cagliari, Cagliari, Italy
fYear
2010
fDate
3-6 May 2010
Firstpage
249
Lastpage
256
Abstract
NoCs performance are usually explored stand-alone, overlooking the impact of the higher communication levels in the ISO OSI micro network stack. Nevertheless, since CPUs have to be relieved of communication management, higher communication levels such as DMA engines necessarily influence the communication performance. In this paper, we investigate how two different DMA implementations, full-duplex and half-duplex, can bias the behavior of a NoC designed for MPP architectures. From our studies, it turned out that a full-duplex DMA is more effective in preventing possible deadlock situations. Moreover, a deep performance analysis of a state-of-the-art NoC, in terms of transactions completion time, queuing time and injection delay, confirms the impact of the DMA in NoC-based MPP platforms, showing the advantages of a full-duplex approach.
Keywords
file organisation; network-on-chip; open systems; parallel processing; ISO OSI micro network stack; NoC performance; completion time transaction; direct memory access; full duplex DMA implementations; half duplex DMA implementation; massively parallel processors; networks on chip; queuing time; Computer architecture; Delay effects; Engines; ISO; Network-on-a-chip; Open systems; Performance analysis; Queueing analysis; System recovery; Tiles; DMA performance bias; deadlock prevention; full-duplex DMA; half-duplex DMA; hybrid switching NoC;
fLanguage
English
Publisher
ieee
Conference_Titel
Networks-on-Chip (NOCS), 2010 Fourth ACM/IEEE International Symposium on
Conference_Location
Grenoble
Print_ISBN
978-1-4244-7085-3
Electronic_ISBN
978-1-4244-7086-0
Type
conf
DOI
10.1109/NOCS.2010.35
Filename
5507541
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