An analytical model for delay and crosstalk estimation in interconnects under general switching conditions

The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In timing analysis, the delay of a critical path should include the effect of crosstalk noise due to the switching of aggressor lines. The fact that the victim and aggressor lines may or may not be switching simultaneously, and the variable strengths of the drivers driving the coupled lines bring in additional levels of complexity to the delay estimation when coupling exists. In this paper, we derive a simple analytical model that takes the effect of different driver strengths into account, to accurately estimate the delay and crosstalk of two coupled interconnect lines. The model is applicable under all switching conditions: simultaneous or nonsimultaneous; in opposite directions or in the same direction