Transition analysis on FPGA for multiplier-block based FIR filter structures

Author

Demirsoy, Siileyman S m ; Dempster, Andrew ; Kale, Hzet

Author_Institution

Dept. of Electron. Syst., Univ. of Westminster, London, UK

Volume

2

fYear

2000

fDate

2000

Firstpage

862

Abstract

This paper presents a study on the power consumption analysis of several multiplier-block based FIR filter structures. Transitions have been counted for the filter structures that were implemented on an FPGA device. The algorithms employed to generate the multiplier-blocks are compared with respect to their power performance. A new term, Glitch Path count, has been proposed and tested for use as an indicator of power consumption. This measure has been shown to be more correlated with the transition counts than the adder-count and logic depth approaches

Keywords

FIR filters; digital arithmetic; digital filters; field programmable gate arrays; logic design; low-power electronics; multiplying circuits; FIR filter structures; FPGA; filter design algorithms; glitch path count; multiplier-block filter structures; power consumption analysis; transition analysis; transition counts; Adders; Algorithm design and analysis; Circuits; Clocks; Digital filters; Energy consumption; Field programmable gate arrays; Finite impulse response filter; Heuristic algorithms; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on

Conference_Location

Jounieh

Print_ISBN

0-7803-6542-9

Type

conf

DOI

10.1109/ICECS.2000.913012

Filename

913012