DocumentCode :
2989514
Title :
Multiple low swing voltage values for CPL, CVSL and domino logic families
Author :
Rjoub, Abdoul ; Koufopavlou, Odysseas
Author_Institution :
Dept. of Comput. Eng., Jordan Univ. of Sci. & Technol., Irbid, Jordan
Volume :
2
fYear :
2000
fDate :
2000
Firstpage :
903
Abstract :
A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed
Keywords :
CMOS logic circuits; adders; logic design; low-power electronics; multiplying circuits; CPL family; CPL multiplier; CVSL family; cascade voltage switch logic; circuit power dissipation reduction; complementary pass transistor logic; domino logic families; internal voltage values; logic circuits; low swing voltage components; low-power design method; multiple low swing voltage values; CMOS logic circuits; CMOS technology; Design engineering; Inverters; Logic circuits; Logic design; Low voltage; MOSFETs; Power dissipation; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2000. ICECS 2000. The 7th IEEE International Conference on
Conference_Location :
Jounieh
Print_ISBN :
0-7803-6542-9
Type :
conf
DOI :
10.1109/ICECS.2000.913022
Filename :
913022
Link To Document :
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