Time-power-area tradeoffs for the nMOS VLSI full-adder

We study the problem of optimizing the pulldown diffusion widths in the one-bit full adder when it is embedded in a regular array, using the simplest possible array multiplier with a delay-time criterion as an example. A local optimization algorithm is used, which varies two parameters at a time along the critical path until a local optimum is found. The analysis routines include the Berkeley tools [10] and the Princeton procedural layout language ALLENDE [11- 12]. Two ways are suggested for optimizing large arrays in practical amounts of time. First, the full-adder cell optimized within a minimum-size array can be used in the large array. This is a good choice because the interior cells of the small prototype have the same boundary conditions as those in the larger array. A second, even faster, method is to approximate the delay time from some simple assumptions about the critical path. Numerical results show that both these methods are effective. We give typical local optima obtained when delay time is minimized, together with power-time tradeoff curves, for the 3×3 and 4×4 array multipliers, using 4µ (λ=2µ) nMOS fabrication parameters, and a 5- parameter random-logic full-adder cell.