The bumping of wafer level packages

The relentless trend for smaller, lighter, cheaper consumer products continues to fuel the demand for new, smaller, efficient electronic packages. In recent years wafer level packaging concepts have emerged, providing multiple design wins in terms of form factor and production costs. Performing all processing at the wafer level prior to dicing provides obvious cost advantages whilst the WLP footprint offers a 1:1 component to package ratio. Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder paste print & reflow techniques can be utilised but the resultant bumps invariably fall below specifications due to process limitations. More commonly, dedicated equipment sets that place pre-formed solder spheres onto the wafer are used. This paper details work undertaken to combine the benefits of standard stencil printer technology with that of solid solder sphere placement to enable the development of a low cost, flexible system for the bumping of wafer level packages. In addition, an alternative print & reflow technique based on an extrusion concept was also investigated. The two techniques are compared for the bumping of a 0.5mm pitch WL-CSP product.