Performance of input-buffered and output-buffered ATM switches under bursty traffic: simulation study

The packet loss probabilities of several alternative input-buffered and output-buffered switch designs with finite buffer space are investigated. The effects of bursty traffic, modeled by geometrically distributed active and idle periods, are explored. It is shown that bursty traffic can degrade switch performance significantly and that it is difficult to circumvent the degradation by merely restricting the offered traffic load. For input-buffered switches, methods that alleviate head-of-line blocking are not effective in lowering packet loss probability under bursty traffic. Packet loss probability is more sensitive under bursty traffic to the specific contention resolution scheme adopted than it is under uniform random traffic. Several interesting, and perhaps unexpected, results are revealed: under bursty traffic, output queueing may have higher loss probabilities than input queuing; under bursty traffic, speeding up the switch operation may have higher loss probabilities than allocating multiple-output ports to each output address; and if buffers are not shared in a fair manner, sharing buffers could make performance worse than not sharing buffers at high traffic loads