A hierarchical based approach for coupling aware delay analysis of combinational logic blocks

In this paper, we present a two-level hierarchical based approach to estimate delays of digital VLSI circuit which takes the interconnects and crosstalk noise into consideration. First, the circuit is partitioned into individual gates driving interconnect lines. Circuit-level characterization is performed for the individual sub-circuits and the interconnects. A static timing simulator has been developed to accurately estimate the delays under the consideration of interconnect coupling. Instead of a single worst delay number, the delay is represented in terms of transition intervals, i.e. the best-case and worst-case delays, by using the information obtained from the circuit level characterization process. Examples show that the simulator produces accurate results compared with SPICE simulations