Performance analysis of asymmetric packet switch modules with channel grouping

The switch modules are studied because they are the key building blocks in large multistage switch architectures. The switch module considered has n inputs and m outputs. A packet destined for a particular output address (out of g) needs to access only one of the r available physical output ports: m =gr. Input-buffered, output-buffered, and unbuffered switch modules are studied. The results show that increasing the number of output ports per output address (r) can significantly improve the performance of buffered as well as unbuffered switch modules. For acceptable performance, the difference in throughput between buffered and unbuffered switch modules is considerable. For buffered switch modules, an interesting observation is that although output-buffered switch modules have significantly better delay performance than input-buffered switch modules when n=gr , the performance difference is diminished as one deviates from these switch dimensions