A VLSI dynamic time warp processor for connected and isolated word speech recognition

A custom designed NMOS VLSI circuit for speech recognition is described. It calculates the distance between a trial utterance and reference templates stored in an attached 32 kilobyte dynamic memory for a vocabulary of up to 200 words. Time warping based on a dynamic-programming minimum distance is employed. Connected words are processed on a continuous real-time basis while isolated word recognition proceeds after the utterance is complete. Multiple stages of pipelining are used in a unique microprogrammed architecture so that template memory bandwidth is fully utilized in the data-intensive distance calculation. Two seperate arithmetic logic units (ALUs) are used, one for numerical data and one for template memory address generation. The basic microinstruction cycle time is 200 nanoseconds. Typical recognition time for a 40 isolated word vocabulary is less than 200 milliseconds.