DocumentCode :
2990467
Title :
Image processing address generator chip
Author :
Eldon, John ; Stroll, Zoltan ; Swartzlander, Earl
Author_Institution :
TRW LSI Products Division
Volume :
10
fYear :
1985
fDate :
31138
Firstpage :
993
Lastpage :
996
Abstract :
Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requires large RAMs, fast multiplier accumulators (MACs), and sophisticated address generators and controllers. TRW is designing a CM36 integrated circuit that generates the necessary control signals and data and coefficient addresses, economically replacing roughly 100 MSI and SSI components. The chip´s target speed of 10 MHz is well matched to commercially available memories and MACs. With its versatile instruction set, the chip efficiently supports all first and second order image transforms, plus two dimensional filtering with a kernel size of up to 225 pixels.
Keywords :
Convolution; Digital filters; Equations; Filtering; Finite impulse response filter; Image generation; Image processing; Interpolation; Nearest neighbor searches; Pixel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
Type :
conf
DOI :
10.1109/ICASSP.1985.1168161
Filename :
1168161
Link To Document :
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