DocumentCode :
2990508
Title :
The systematic exploration of pipelined array multiplier performance
Author :
Hauck, Charles E. ; Bamji, Cyrus S. ; Allen, Jonathan
Author_Institution :
Massachusetts Institute of Technology, Cambridge, Massachusetts
Volume :
10
fYear :
1985
fDate :
31138
Firstpage :
1461
Lastpage :
1464
Abstract :
The throughput of a combinational array multiplier is shown to be asymptotically suboptimal using performance measures derived from VLSI models of computation. Applying a systematic transformation called retiming, a class of asymptotically optimal pipelined array multipliers is obtained. The optimum circuit performance within this class must be deternmined empirically through repeated iterations of multiplier layout generation, circuit extraction, and electrical simulation. The structure of these pipelined multipliers facilitates such an empirical investigation by admitting very regular layouts that can be generated quickly and interactively.
Keywords :
Circuits; Computational modeling; Costs; Laboratories; Military computing; Parallel processing; Pipeline processing; Throughput; Very large scale integration; Winches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
Type :
conf
DOI :
10.1109/ICASSP.1985.1168163
Filename :
1168163
Link To Document :
بازگشت